Packet switching provides a known solution to problems where the information to be transmitted occurs in short, high-rate burst with long pauses in between bursts. The use of packets allows efficient utilization of the switching and transmission facilities. A packet consists of a predetermined number of data bits, together with synchronization and other identifying data. The use of low-bit rate encoding techniques coupled with not transmitting silent periods results in digitally-encoded voice information having characteristics which are very similar to those of data information--short, high-rate busts with longer pauses in between bursts. Despite the fact that voice information has not been considered well suited for transmission in the form of packets, the transmission of voice information in the form of packets is a desirable result. Not only would the packetizing of low-bit rate voice encoded information result in a more economic and more effective switching system, it would also allow the introduction of a totally integrated voice and data packet system. Such an integrated system would allow the effective implementation of enhanced voice and data services for example on a nationwide basis.
A principal reason for not considering voice information well suited for transmission in the form of packets is that voice information cannot tolerate long delays during transmission. Delays in excess of 250 milliseconds have been found to be unacceptable for voice communication. In contrast, delays of many seconds for data are not objectionable.
Prior art systems for switching packets have been rather small systems consisting of only a few hundred nodes and are designed to switch packets containing data information. In addition, such systems have employed large computers using sophisticated software packages to perform the packet switching functions at each node within the system. These systems have utilized complex control protocols to handle the problems of error recovery and flow control and to perform the route identification functions. As a result, the prior art systems have had a limited packet handling capability being capable of handling only a few thousand packets per second. A recognized disadvantage in such systems is that the complex control protocols introduce a large amount of delay into the transmission of a packet. For example, when a packet was received the computer had to examine the logical address to determine the destination of the packet and then take the necessary steps to transmit the packet to that destination. That process involved the time consuming steps of translating the logical address into a physical address designating the transmission link over which the packet was to be retransmitted and then actually retransmitting the packet after performing the necessary error and flow control. Because of the large number of time consuming steps required to translate the logical address into the physical address, the prior art systems required a large number of buffers to store packets which were awaiting address translation and retransmission. This large number of buffers increased the size of the prior art systems, and introduced a large amount of time delay. Since the time delay was introduced at each switching node, the total delay of a particular packet depended on the number of switching nodes through which the packet was transmitted. For a large number of nodes, the delay became quite unacceptable, with respect to the transmission of packetized voice.
The prior art systems have proven non-desirable for implementing a national telecommunication switching network function because of the delay which they would introduce and because such systems would be physically too large, complex, and expensive if expanded to perform this function.
In light of the foregoing, it can be seen that there exists a need for a packet switching system which can transmit packets with a minimum amount of delay. The architecture of the packet switching system should be such that the time consuming logical-to-physical address translation functions are not performed at each node of the packet switching system. In addition, the architecture of the packet switching system should be such that a high capacity system can be constructed which has a reasonable physical size and desirably allow the utilization of very large scale integration (VLSI).